1. Field of the Invention
This invention relates to an apparatus and method for performing chemical-mechanical polishing ("CMP") upon a substrate and for accurately terminating CMP.
2. Description of Related Art
During a wafer fabrication process, multiple integrated circuits are formed upon frontside surfaces of each of several semiconductor wafers processed somewhat concurrently. Each integrated circuit consists of electronic devices electrically coupled by conductive traces called interconnects. Interconnects are patterned from conductive layers formed on the surface of a semiconductor wafer. The ability to form stacked layers of interconnects has allowed more complex circuits to be implemented in and on relatively small surface areas of silicon substrates. The individual interconnect levels of multilevel interconnect structures are separated by layers of electrically insulating materials (i.e., interlevel dielectric layers).
As the number of interconnect levels is increased, the stacking of additional interconnect layers on top of one another tends to increase the elevational disparities in frontside surface topographies. Problems arise when attempting to form interconnects upon rugged frontside surface topographies. Abrupt elevational changes in the frontside surface topography of a semiconductor wafer typically occur at or near lateral edges of underlying patterned features, e.g., interconnects. The tendency of layers formed upon the surface topography of a semiconductor wafer to be thinner over such abrupt elevations changes (i.e., "steps") is referred to as the "step coverage" problem. In additional to the step coverage problem, large and abrupt elevation disparities lead to depth of focus problems. Depth of focus problems become an issue during the lithographic process in which layers are patterned across a semiconductor topography. A major factor in the processing of integrated circuits with submicron device dimensions is the limited depth of focus of the optical steppers used to pattern circuit features. In order to obtain maximum resolutions, imaging surfaces must be fairly planar with a suitable elevational disparity less than about 0.5 microns. Accordingly, interlevel dielectric planarization techniques must be employed in order to make imaging surfaces substantially planar.
CMP is a popular method of planarizing the upper surface of a layer (e.g., an interlevel dielectric layer) formed upon the frontside surface of a semiconductor wafer. CMP combines chemical etching and mechanical buffing to remove raised features upon the frontside surface of the semiconductor wafer. During an exemplary CMP process, the semiconductor wafer is inverted whereby the frontside, circuit embodied surface faces downward upon a polishing pad preferably saturated with a liquid slurry containing abrasive particles and a mild etchant chemical which softens or catalyzes the exposed material being planarized. The polishing pad is fixedly attached to a rotatable table or platen. When the rotatable table or platen is set into motion, elevationally extending portions of the frontside surface are removed by combined chemical softening of the exposed surface material and physical abrasion brought about by relative movement between the polishing pad and the frontside surface.
In CMP operations, it is important to be able to detect when sufficient planarization of the frontside surface topography has been achieved and to stop the CMP process in order to avoid removing too much material at the frontside surface (e.g., interlevel dielectric material). FIG. 1a is a side elevation view of an exemplary CMP apparatus 10 including elements used to detect end point conditions. A backside surface of a semiconductor wafer 12 is held against a rotatable polishing wheel 14. An opposed frontside surface of semiconductor wafer 12 has multiple layers of select materials formed thereupon. The frontside surface of semiconductor wafer 12 is brought into contact with a layer of an abrasive polishing fluid (i.e., slurry) existing between semiconductor wafer 12 and polishing pad 16. Polishing pad 16 is fixedly attached to a rotatable platen 18. Polishing wheel 14 may include a hollow shaft 20 attached at its center of rotation. During use, shaft 20 may be rotated by motor 22 through drive train 24, and platen 18 may also be rotated such that polishing pad 16 moves, orbits and/or rotates relative to semiconductor wafer 12.
Apparatus 10 may also include a light source 26 and a light detector 28. Light source 26 emits an incident beam of light 30 directed through hollow shaft 20 substantially perpendicular to the backside surface of semiconductor wafer 12. Incident light beam 30 includes one or more wavelengths at which semiconductor wafer 12 is substantially transparent (e.g., infrared radiation having longer wavelengths than visible light). A portion of incident light beam 30 reflected back from semiconductor wafer 12 and toward light detector 28 forms a reflected light beam 32.
FIG. 1b is an exploded view of the portion of FIG. 1a illustrating formation of reflected light beam 32 from incident light beam 30. In FIG. 1b, a first dielectric layer 34 exists directly upon the frontside surface of semiconductor wafer 12. Interconnects 36 are formed upon first dielectric layer 34, and a second dielectric layer 38 is formed over interconnects 36. An exposed surface of second dielectric layer 38 is being planarized using apparatus 10. A layer of an abrasive slurry 40 is interposed between second dielectric layer 38 and polishing pad 16 to effectuate planarization.
A portion of incident light beam 30 is reflected back toward light detector 28 at the backside surface of semiconductor wafer 12 and at each interface between the layers formed upon the frontside surface of semiconductor wafer 12, forming reflected light beam 32. These reflected portions interfere with one another, adding together to produce a greater intensity when they are in phase with one another and subtracting from one another to produce a lesser intensity when they are out of phase. Of prime importance is a component 42 of reflected light beam 32 reflected from the exposed surface 44 of second dielectric layer 38. When exposed surface 44 is not substantially planar, the contribution of component 42 to reflected light beam 32 is negligible. When exposed surface 44 becomes substantially polished and planar during the CMP operation, however, the contribution of component 42 to reflected light beam 32 is significant. As the CMP operation is continued after second dielectric layer 38 becomes polished and substantially planar, relatively small but detectable cyclic changes begin to occur in the intensity of a monitored wavelength of reflected light beam 32 resulting from the thinning of second dielectric layer 38 and the consequent phase changes of component 42. See, e.g., U.S. Pat. No. 5,499,733 (herein incorporated by reference).
FIGS. 1a-b represent a highly simplified example in which semiconductor wafer 12 includes only a single interconnect layer. Modern integrated circuits typically have several levels of interconnects separated by one or more layers of interlevel dielectrics. Contributions to reflected light beam 32 from reflections at the multiple interfaces between the interlevel dielectric layers represent a substantial background noise level against which relatively small cyclic changes in the intensity of reflected light beam 32 must be detected. The result is a high degree of ambiguity in CMP end point detection which increases with the number of integrated circuit interconnect levels.
It would thus be desirable to have an automatic CMP end point detection apparatus and accompanying method which: (i) minimize the number of contributions influencing end point detection, and (ii) make end point detection independent of the number of integrated circuit interconnect levels. The desired apparatus and method would allow CMP processes to be more closely controlled, resulting not only in better step coverage and depth of focus but also providing closer interlevel dielectric thickness tolerances and more predictable interconnect electrical characteristics.